Electronic products (e.g., wearables, mobile phones, smart phones, tablet computers, etc.) are continually being designed to be more flexible, compact and portable. Therefore, it is extremely important to reduce the form factor, z-height and weight of the electronic devices that are included in mobile products.
One of the concerns that can arise as things are made smaller is signal integrity issues. As examples, channel impedance discontinuity and crosstalk are common issues that are continually addressed during high-speed package and PCB design.
In some electronic devices, signal crosstalk, reflection and loss are common issues that occur in conventional systems which include differential pairs of conductors. Signal crosstalk, reflection and loss may have negative design impacts by limiting bus design scaling (e.g., frequency, power, silicon real-estate, package layer-count and channel length).
Conventional solutions that seek to mitigate signal integrity issues typically require some form of design trade-off. One or more of these design trade-offs usually constrain enabling smaller and more flexible form factor high-speed packages and PCBs.
As a first example, high-speed packages and PCBs may increase the layer count and/or Z-height of the high-speed packages and PCBs. The number of signal routing layers and grounding layers may be increased to alleviate the signal integrity issues (e.g., due to breakout/congested routing areas or routing-over-void/split-plane areas).
As a second example, high-speed packages and PCBs may reduce routing density (i.e., increase in routing pitch). The layout of high-speed packages and PCBs may be optimized to reduce signal integrity issues by keeping interconnects with at least 2×-spacing away from one another to (i) reduce crosstalk; and (ii) have a transition to other routing layer to avoid routing over-void/split-plane areas.
As a third example, high-speed packages and PCBs may require an increase in power consumption. This increase in power consumption is typically combined with circuit patterns where active crosstalk cancellation, loss equalization and terminations are applied to mitigate crosstalk, reflection and loss.
Digital devices and analog devices commonly co-exist in a spatially close proximity in many electronic devices such as wearables, IOT devices, cellular phones, tablets and client PCs. Electromagnetic interference (EMI) typically occurs between devices with direct or harmonic frequency overlap.
The presence of direct or harmonic frequency overlap undesirably increases the risks for normal functionality of the electronic device. An EMI shield that is made from materials with good conductivity or magnetic permeability is usually used to reduce the EMI risks.
One of the current EMI shielding techniques that is commonly used includes incorporating a box shield. However, box shields typically have a minimum size constraint which can be difficult to adequately incorporate into smaller electronic devices.
Another current EMI shielding techniques that is commonly used includes incorporating a conformal shield. The conformal shield is usually added to a conventional electronic component covering mold by a sputtering, coating, plating or printing process to create a metal layer outside of the mold. However, a conformal shield requires an additional metal layer deposition process thereby adding unwanted costs.
Therefore, a need exists for an EMI shielding technique that reduces the effects of direct or harmonic frequency overlap. Reducing the effects of direct or harmonic frequency overlap may address channel impedance discontinuity and crosstalk issues within close proximity electronic components while minimizing any design trade-offs.